This invention is in the field of solid-state semiconductor memories. Embodiments of this invention are more specifically directed to memory cells and architectures for read-only memories.
Non-volatile solid-state memory devices are now commonplace in many electronic systems, particularly in portable electronic devices and systems. Mask-programmable read-only memories (ROMs) constitute one conventional type of non-volatile semiconductor memory. While read/write non-volatile memory technology such as electrically erasable programmable “read-only” memory (EEPROM) devices, “flash” EEPROMs, ferroelectric random-access memories (FRAMs) are currently available, mask-programmable ROMs continue to be attractive due to their extremely small cell sizes and fast read time (for purposes of this description, mask-programmable ROMs will be referred to herein simply as “ROMs”, it being understood that EEPROMs and other programmable memories also operate as “read-only” memories).
FIGS. 1a and 1b illustrate the arrangement of conventional mask-programmable ROM cells. FIG. 1a is a simplified electrical schematic of a 2×4 portion of a conventional ROM array, showing the arrangement of ROM cells 20,0 through 21,3 in two rows and four columns. In this conventional example of a ROM array, cells 20,0 through 20,3 are in the same row, and as such receive word line WL0 for that row, while cells 21,0 through 21,3 are in the same row and receive word line WL1 for that row. Cells 20,0, 21,0 are in the same column, and are each coupled to bit line BL0, while cells 20,1, 21,1 are coupled to bit line BL1 for their column, cells 20,2, 21,2 are coupled to bit line BL2 for their column, and cells 20,3, 21,3 are coupled to bit line BL3 for their column. Bit lines BL0 through BL3 are each connected to sense amplifier 6 and precharge circuitry 3 via column decode multiplexer 5. Alternatively, precharge circuitry 3 may be connected to all bit lines BL0 through BL3 (e.g., on their opposite ends from column decode multiplexer 5). A word line decoder (not shown) drives one of word lines WL0, WL1 according to a decoded row address. Column decode multiplexer 5 receives decoded address signals Y[0], Y[1], Y[2], Y[3], in response to each of which the corresponding one of bit lines BL0 through BL3, respectively, is coupled to sense line SL and sense amplifier 6.
In this conventional example, each of cells 2 is constructed as a single re-channel metal-oxide-semiconductor (MOS) transistor having its gate connected to the word line WL0, WL1 for its row, and its source at ground (Vss). The drain of the MOS transistor of each cell 2 may or may not be connected to the bit line BLx for its column, depending on the programmed data state for that cell 2. In the example of FIG. 1a, cells 20,1 and 21,0 are each programmed to a “0” level, by virtue of their transistor drains being connected to bit lines BL1, BL0, respectively. Conversely, cells 20,0 and 21,1 are each programmed to a “1” level, by virtue of their transistor drains being left floating, and not connected to bit line BL0, BL1, respectively.
In the operation of the conventional example of FIG. 1a, one of bit lines BL0 through BL3 is selected by column decode multiplexer 5, for example in response to the two least significant bits of the column address; this selection similarly selects every fourth column throughout the array. At the beginning of a read cycle while word lines WL0, WL1 remain inactive low, precharge circuitry 3 precharges the selected bit lines to a high voltage and then releases those selected bit lines, allowing them to electrically float. Following bit line precharge, one of word lines WL0, WL1 is energized in response to the row address, turning on the n-channel MOS transistors of cells 2 in that row. Those cells 2 in the selected row and the selected columns that are programmed to the “0” state will begin pull their respective bit lines toward Vss from the precharged level. For example, if bit line BL1 is selected and word line WL0 is then driven active high, the n-channel transistor in cell 20,1 will discharge the precharged level at bit line BL1 because cell 20,1 is programmed to its “0” state. Conversely, those cells 2 in the selected row and columns that are programmed to the “1” state are disconnected from their respective bit lines, and cannot pull those bit lines from their precharged voltage toward Vss. For the example of cell 20,1 in FIG. 1a, 1f bit line BL1 and word line WL1 are selected, bit line BL1 will remain at its precharged level because the “1” state has been programmed. After a sufficient time for the selected bit line BL0, BL1 to reach its eventual level, sense amplifier 6 is enabled to detect the level at the selected bit line BL0, BL1.
As evident from FIG. 1a, the construction of cells 2 is quite simple—each cell 2 consists of only a single transistor, with its drain either connected or not connected to bit line BLx for its column. FIG. 1b illustrates, in plan (layout) view, the construction of four cells 20,0 through 21,1 according to a conventional approach. In this construction, each cell 2 is constructed within an active region (e.g., a p-type well, or a p-type region of the substrate surrounded by isolation dielectric in the conventional sense). Word lines WL0, WL1 are constructed of polycrystalline silicon or another gate material, and extend across the active regions to serve as the gate electrode of the n-channel transistors of cells 2 in the corresponding rows. The active surfaces on either side of word lines WL0, WL1 are doped n-type, to form source regions 9s and drain regions 9d of those transistors in the conventional self-aligned manner. A metal conductor providing ground voltage Vss extends across each row of cells 2, parallel to word lines WL0, WL1, making contact to each source region 9s through via 13. Bit lines BL0, BL1 are formed in a different metal layer from that providing ground voltage Vss, and extend perpendicularly across cells 2 in corresponding columns. In this example, bit line BL0 extends vertically (in the view of FIG. 1b) across cells 20,0, 21,0, and bit line BL1 extends across cells 21,0, 21,1.
Each cell 2 is programmed by the presence or absence of a via 11 between its drain region 9d and its corresponding bit line BL0, BL1. In this example, no via 11 is provided for cells 20,0, 21,1, and as such neither of those cells is connected to its corresponding bit line BL0, BL1; these cells 20,0, 21,1, are thus programmed to a “1” data state. Conversely, a via 11 is provided in each of cells 20,1, 21,0, connecting drain region 9d to bit lines BL0, BL1, respectively. These cells 20,1, 21,0 are thus programmed to a “0” data state.
In this conventional construction, the read performance of ROM cell 2 is determined by the current conducted by its n-channel transistor for the “0” data state, as it is this current that determines the time required for cell 2 to discharge the precharged bit line to a voltage that can be accurately and reliably sensed by sense amplifier 6. As is fundamental in the MOS field, the current drive of the cell transistor is directly proportional to the transistor channel width/length ratio. FIG. 1b shows the transistor channel width CW and channel length (i.e., gate width) GW for cell 20,0. For maximum device density, and thus minimum chip area required for the ROM resource, it is desirable to construct cells 2 using minimum size MOS transistors available for the manufacturing technology.
It has been observed, in connection with this invention, that the scaling of ROM transistors at technology nodes of 45 nm and smaller may be limited. One difficulty is the increased device variability at these small feature sizes, particularly in connection with the variability of threshold voltage. At these extremely small feature sizes, effects such as random dopant fluctuations, stress effects, and line edge roughness can cause significant variations in threshold voltage from transistor to transistor. This threshold voltage variability is reflected in significant variation in read current from cell-to-cell in the same array. This variation necessitates relaxation of design parameters to account for the worst case read current, for example by not scaling the ROM cell transistors along with the minimum transistor sizes of the manufacturing technology, or by reducing the bit line length, or both. These relaxed parameters result in reduced performance and larger chip area than would otherwise be expected at the available technology node.